(1) Field of the Invention
The present invention relates to a mask ROM (read only memory), and more particularly, to a method of fabricating high density multiple states mask ROM cells.
(2) Description of the Prior Art
Read-only-Memory (ROM) circuits are used to permanently store code in electronic equipment, such as computers, microprocessor systems and the likes. The code or information stored in the ROM circuit is non-volatile when the power supply is powered off.
Memory cells are fabricated on a portion of the ROM device consisting of an array of single transistor, typically field effect transistor (FET), arranged in rows and columns. The arrays of FETs are built by first forming an array of closely spaced parallel electrically conducting line regions in the semiconductor substrate called "bit lines". The bit lines serve as the source/drain regions of the FETs, and also serve as the electrical interconnections to the peripheral circuits for outputting the stored binary data. The buried bit lines are usually formed in the semiconductor substrate by ion implantation and a thermal oxide is then grown on the semiconductor substrate forming the gate oxide of the FET between the bit lines. The thermal oxide also provides the electrical insulation layer over the bit lines. A plurality of closely spaced parallel conducting line called "word lines", usually formed from a doped polysilicon layer, are then formed on the semiconductor substrate having an orthogonal direction to the buried bit lines. The word lines serve as the gate electrode of the FETs and also function as the electrical interconnection to the peripheral address decode circuit. The array of ROM cells are then coded with information, such as micro-instruction, by permanently rendering selected transistor non-conducting during processing while non-coded cells can be switch on, when accessed by way of the address decode circuits. The coded information represented by a change or no change in the voltage level at the output circuit are used to represent the binary 1's and 0's. The code for the ROM is introduced during device processing by using a ROM code mask during one of the processing steps.
In a conventional mask ROM device, there are only two states, which are the "ON" state and the "OFF" state. The "OFF" state is typically defined by code implantation to increase the cell threshold voltage (Vth) is above 5 Volt, while the "ON" state is defined the cell Vth to be below 1 Volt. In a high density mask ROM (32 M or 64 M), a conventional two state mask ROM will consume a large wafer area due to the large chip size. If one memory cell can store more than three kinds of data, called a multiple states mask ROM, it is possible to greatly increase the storage capacity of a mask ROM. For example, if one memory cell can store four kinds of data, it is possible double the storage capacity in one chip without increasing the chip area.
A traditional method to fabricate a multiple states mask ROM cell, in the manner that changes the threshold voltage of memory cell transistors is given in U.S. Pat. No. 5,585,297 issued on Dec. 17, 1996. A plurality of ion implantation stages using boron ions is performed incorporating with using a plurality of different mask patterns and different dosage level. However, the high dose boron coding implantation will result in a lower junction breakdown performance of the coded FET and a very high band-to-band leakage current between the adjacent cells as stated in U.S. Pat. No. 5,683,925, issued on Nov. 4, 1997.
An alternative method is proposed in U.S. Pat. No. 5,556,800 issued on Sep. 17, 1996. In this method, the channel region of cell transistor is divided into dual parts; one divided part having a different gate oxide thickness to the other, and thus a different transitivity for implanted ions. Namely, the gate electrode has different characteristics of a drain current corresponding to a given gate voltage in the channel regions adjacent to each other. However, it is difficult to control the uniformity of device performance, due to the misalignment of photo mask.
Another method to form a tri-state mask ROM cell is proposed in U.S. Pat. No. 5,693,551 issued on Dec. 2, 1997. This invention makes use of a liquid-phase deposition process to form insulating blocks filling trenches among the word lines. After removing the shielding layer (photoresist) to reveal sidewalls, silicon nitride spacers are formed on the sidewalls. Some of the silicon nitride spacers are selectively removed to form different channel length of the word lines. The coding implantation is performed through polysilicon and gate oxide into semiconductor substrate to form a tri-state ROM cell. This method could prevent the occurrence of the misalignment, however, it is not compatible to use the liquid-phase deposition method in the modern integrated circuits fabrication.
The multi-state mask ROM cells can also be formed by using a stacked CVD oxide architecture, as shown in U.S. Pat. No. 5,576,573 issued on Nov. 19, 1996. This invention uses a number of CVD oxide deposition, masking and etching steps to form a multi-state mask ROM cell. However, this method will increase the fabrication cost and cycle time due to the more processing steps as compared to the other method.